1. Field of the Invention
The present invention relates to memory circuits and, more particularly, to word line driver circuits which are connected to the output terminals of decoder circuits therefor.
2. Description of the Prior Art
For driving the word line in an array of memory cells, which are selectively addressed by decoder circuits, there are generally employed two types of driver circuits.
A first type is a push-pull buffer type depicted in FIG. 1. The word line driver circuit is shown in broken lines 5 connected between a decoder circuit 1 and an array of memory cells 4. The driver circuit includes a pair of MOSFETs 2 and 3 connected between potential - VDD and ground. To the gate electrodes of these MOSFETs the output of the decoder circuit is supplied directly and through an inverter 6, as shown.
For this arrangement, upon the supply of a gating potential at the output of decoder 1 for turning MOSFET 2 on, the MOSFET 2 will be rendered conductive, while because of inverter 6, MOSFET 3 will be turned off. With MOSFET 2 having been rendered conductive, the potential supplied to the drain thereof (-VDD) will be coupled to the word line for supply to the memory cell array 4.
On the other hand, in the absence of a gating potential supplied at the output of a decoder circuit 1, MOSFET 2 will be turned off by the output level (0 volts) from the decoder circuit 1, which, by virtue of inverter circuit, will cause a sufficient gating potential to energize the MOSFET 3. With MOSFET 3 turned on, the common reference potential (ground) will be applied to the word line 7; thereby preventing the word line driver circuit 5 from floating.
With this type of arrangement, however, an inverter circuit, which serves no function other than to provide an inverted signal, is required and MOSFET 3 operates in the dependence upon the output of the decoder circuit 1. As a result, the integration density of the overall memory circuit suffers.
Another prior art type of word line driver circuit arrangement employs a pair of MOSFETs with a chip-enable signal and an inverted chip-enable signal supplied to both MOSFETs. Such a circuit is illustrated on page 6 of the publication "Silicon Gate MOS LSI RAM 1103" published by Intel Corporation, 1971, particularly Page 6 thereof. Also, this type of circuit is described in the manual "Semiconductor Memories", Bulletin CW-806, Videotape Course Workbook, by Texas Instruments Incorporated, 1972, particularly Pages 5-17 thereof.
This circuit is illustrated in FIG. 2 of the drawings wherein, as in the circuit of FIG. 1, a pair of MOSFETs 2 and 3 are connected between a decoder circuit 1 and a memory cell array 4. MOSFET 2, rather than being connected to a fixed potential has its drain connected to receive a control signal CE (chip-enable), while a not-chip-enable signal CE is applied to the gate of MOSFET 3. These signals will be supplied simultaneously to the word driver circuits for selectively turning MOSFET 2 on while MOSFET 3 is turned off and vice versa. This circuit is advantageous relative to the circuit of FIG. 1 in that the integration density can be improved by elimination of the inverter circuit 6.
However, the memory cell array 4, coupled to the driver circuit 5, in the arrangement of FIG. 2, is subject to mis-operation where the word line 7, which has not been selected by the decoder circuit, floats, and accordingly, may pick up noise sufficient to select a memory cell. Namely, in the absence of a gating potential at the output of the decoder circuit 1, MOSFET 2 will be turned off, and accordingly, if the CE input to MOSFET 3 is inverted, namely, the gate of MOSFET 3 is not turned on, the word line supplied to the memory cell array 4 will float.
When the potential of the floating word line 7 reaches or exceeds the level of the address signal required for accessing a memory cell due to noise, a gate of one of the circuits within the memory cell may be rendered conductive thereby causing misoperation of the circuit and an inadvertent addressing of an undesired memory cell.
Accordingly, while the circuit of FIG. 2 may enhance the density of integration of the memory circuit proper, it does have its drawbacks in that it is subject to misoperation.